The present invention relates to semiconductor integrated circuit devices as well as their fabrication, and more particularly to isolated ultra-thin Si channel devices having a channel thickness of less than about 20 nm and a method to fabricate such isolated ultra-thin Si channel devices.
In semiconductor processing, silicon-on-insulator (SOI) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a buried insulating layer electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing layer, which is oftentimes referred to in the art as the SOI layer, is generally the area in which active devices such as transistors are formed. Devices formed using SOI technology offer many advantages over their bulk Si counterparts including, for example, higher performance, absence of latch-up, higher packing density and low voltage applications.
In the semiconductor industry, the SOI thickness has been scaled down in every SOI device technology generation. Current technology trends are for providing SOI devices that have ultra-thin Si channels. Ultra-thin Si channel devices, which are formed in the top Si-containing layer of an SOI substrate, have demonstrated excellent scalability. The term “ultra-thin” is used throughout this application to denote a channel region having a vertical thickness of less than about 20 nm.
Although the ultra-thin Si channel device is acceptable, device isolation is one of the challenges for the manufacturer. The problem occurs during wet cleaning which can undercut the thin SOI layer and create a region under the active area that can be filled with gate polySi during deposition. Since the poly-Si is trapped under the active area, it cannot be etched during the gate stack etch and thus causes shorting between the gates lying on the same active area. This problem can be divided into two cases: The first case is when the shallow trench isolation (STI) is higher than the active device region, and the second case is when the STI is lower than the active device region. Both cases can lead to shorting if prior art processing is employed.
FIGS. 1A-1H show the basic processing steps that are employed in forming a transistor having an ultra-thin device channel. FIG. 1A shows an initial structure of the prior art process in which pad stack 18 is formed atop an upper surface of an SOI substrate 10. The SOI substrate 10 includes a bottom Si-containing layer 12, a buried insulating layer 14 and a top Si-containing layer 16. The pad stack 18 includes an oxide layer 20 and a nitride layer 22 overlying the oxide layer 20.
FIG. 1B shows the structure that is formed after trench 24 has been formed into the structure shown in FIG. 1A. The trench 24 is formed through nitride layer 22, oxide layer 20, and top Si-containing layer 16 stopping within the buried insulating layer 14. The structure shown in FIG. 1B is formed by lithography and etching.
Next, the pad oxide layer 20 is removed utilizing a conventional selective wet etch process in which a chemical etchant such as hot hydrofluoric (HF) acid is employed to remove the oxide from the structure. After the pad oxide is removed, a sacrificial oxidation and sacrificial oxide removal process is carried out. The oxides are typically formed by thermal processes, while the oxide removal is accomplished by etching in a wet HF acid mixture. Additionally, many state of the art circuits require multiple gate oxide thicknesses. Multiple gate oxide processes include thermal oxidation and wet etching. The wet etching steps of the prior art process result in an undercut region 28 being formed in the buried insulating layer 14; see FIG. 1E. Note that the undercut region 28 is located beneath the top Si-containing layer 16 of the SOI substrate 10.
A gate oxide layer 30 is then formed via oxidation providing the structure shown in FIG. 1F and thereafter a layer of polysilicon 32 is formed via deposition providing the structure shown, for example, in FIG. 1G. The next step in the prior art process comprises a gate stack etch which provides the structure shown in FIG. 1H; in this figure, reference numeral 34 represents the gate polysilicon.
Because of the undercut region 28 that is formed utilizing this prior art process, polysilicon stringers 36 remain in the regions of undercut. The poly silicon stringers 36 that remain in the trench cause gate shorting which limits the use of prior art ultra-thin Si channel devices. FIG. 2 shows a top-down view of the prior art structure produced using the processing steps shown by FIGS. 1A-1H.
In view of the undercut problem that results in stringer formation in the prior art process to isolate ultra-thin Si channel devices, there exists a need for providing a new and improved method to isolate ultra-thin Si channel devices that prevents the formation of polysilicon stringers.